Ինստիգեյթ Կիսահաղորդիչներ

Աշխատանքի նկարագրություն՝

• Write verification specifications, verification plans, and documentation

• Develop test bench and automate regression plans

• Be responsible for simulation, verification, and debugging of logic designs (schematics, RTL)

• Be responsible for developing test-benches , test cases and verification flow components for Soc based FPGA

• Develop tests with software/firmware flow used in SoC FPGA verification

• Develop Behavioral models using Verilog and SystemVerilog

• Develop Coverage driven Verification flows

• Develop and complete block-level verification and contribute on the test development for SoC FPGA fullchip level verification

• handle complex Block and Subsystem Verification platform

• debug the logic designs for design intent

• Bring a self-motivated and enthusiastic approach that will achieve any new requirements and overcome all challenges

/am/senior-engineer-for-fpga-development-5

Աշխատանքային պարտականություններ

- design/implementation/integration of IP modules, creation of HW/SW verification/validation test-benches
- debugging Verilog RTL, generated bit-streams, building CAD flows for EDA tools
- investigation of benchmark and complex designs for QoR analysis, find QoR outliers
- coding with C/C++ for firmware/drivers, develop IFS/GUI with C++/QT,  review/improve the existing codes
- preparing necessary technical documentation
- communicating effectively with team members handling communication/conference calls with customers at late hours if required
- handle assignments in both R&D and QA projects
- applying best practice techniques: monitor and input into the organization's standards and processes
- work as a part of the team: help team to grow in knowledge, participate in management discussions, help to grow junior members of the team, support long-term company growth

Անհրաժեշտ հմտություններ

• Hands on project experience in RTL Verification

• Strong knowledge on digital fundamentals and understanding of FPGA/ custom chip flow

• Hands on knowledge on Verilog and SystemVerilog

• Hands on knowledge in C/ C++ language

• Experience in FPGA programming and related software usage with Firmware

• Exposure to SVF and STAPL/JAM: Adaptive FPGA Programming is a plus

• Good Knowledge in logic design and analysis

• Experience with UNIX shell scripting or Perl scripting

• Experience in Verilog, SystemVerilog, UVM

• Exposure to SoC FPGA flow concepts

• Exposure to Gate Level Simulations and Firmware Verification

• Exposure to knowledge on System Verilog Assertions, Functional Coverage and Scoreboard

• Experience with leading edge simulator tools is recommended

• Good analytical and problem solving skills

• Excellent written and verbal communication in English.

Պահանջվող թեկնածուի մակարդակը: Ավագ

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