Synopsys Armenia

Job description:

We’re looking for a Senior Layout Design Engineer to join our team. On this role you’ll acquire and develop competences in all layout design activities, ranged from layout entry, floorplanning verification and quality validations. The focus of our team is developing high speed SerDes physical interface and design all the necessary analog blocks to support it ranging from basic blocks to complex structures that touch the boundary of chip interface. Does this sound like a good role for you?

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Job responsibilities

• Requires a MSc in Electrical or Computer Engineering (or equivalent) with solid background on transistor level and 5+ years working experience in layout circuit design.
• Possesses knowledge in deep submicron CMOS technologies.
• Exercises good judgment in selecting efficient/robust methods and techniques to layout floorplan and validation.
• Design for porting (i.e. design to enable ease moving layout across multiple foundry nodes).
• Knowledge of signal integrity issues and techniques to mitigate ESD, latchup (i.e. clock/data routes, differential routing, shielding, well distance, substrate biasing).
• Familiarity with custom digital layout (i.e. high speed digital paths).
• Knowledge of layout effects and design for reliability (i.e. matching, reliability, proximity effects, EM, IR, etc.).
• Good written and verbal communication skills and problem solving skills.
• Builds productive internal/external working relationships. Networks with senior internal and external personnel in own area of expertise.
• Contacts are primarily within business unit and occasional organizational and external customer contacts on routine matters.
• Has familiarity with UNIX operating systems and IC design tools.
• Good at problem solving. Presents critical judgement.
• Good written and verbal English communication skills.
• Organizational skills are essential.
• Self-motivated personality.

Required qualifications

• Familiarity with layout of analog and mixed signal CMOS circuits.
• Contributed to the development of complex layout integrated circuits.
• Knowleagable about signal integrity (ie. clock/data routes, differential routing, shielding).
• Implementation of ESD design constraints, latch-up risk mitigation.
• Layout design for reliability (ie. EM, IR, etc.)
• Design to optimize for parasitic layout effects (ie. matching, reliability, proximity effects, etc.).

Preferred Experience

• Knowledge on Synopsys EDA tools.
• Familiar with Unix and scripting languages (TCL, Python).

Required candidate level: Senior

Additional information